As data processors are required to run at continually increasing frequencies, circuits previously adequate to perform a given function are no longer able to perform at the increased operating frequencies and thus become obsolete for use. In one example, memories are often integrated together with a central processing unit (CPU) allowing for efficient CPU execution of operations by reducing the number of required external accesses associated with a given access. Over time, memories which were once designed to operate at similar frequency to the CPU are now functioning at substantially lower frequencies. Though new memories with increased speed capabilities are also being developed, it is often desirable to maintain the slower memories in a data processor to reduce overhead costs associated with designing and implementing the new faster memories. However, other issues often arise as to the compatibility of the memory with a new clock provided in the data processor.
Specifically, memory systems are designed with a specific access time requirement. During an access a memory system typically requires a predetermined time to decode, precharge, sense, and output an appropriate data value. Operation outside of the predetermined time may result in the memory system providing erroneous data which can not be used by the data processor. To avoid this problem, memory systems have been developed which utilize self-timed memories. Such a prior art system is demonstrated in FIG. 1.
Self-timed memories, although independent of the system clock frequency, are dependent on the processing and physical layout of the memory system. Additionally, self-timed memories typically require additional design time and silicon area. In memory systems which are controlled by the system clock or some derivative thereof, the predetermined access times are independent of processing and physical layout; the present invention addresses the latter type of memory systems.
In FIG. 1, a self-timed memory 32 is controlled by internally generated control signals, examples of such internally generated signals include an internally generated sense signal, an internally generated decode, and a precharge signal. As each of these signals and other control signals not illustrated in detail herein is generated in response to a predetermined time period, self-timed memory 32 is only able to provide correct data at a fixed time interval. This data is provided to data register 34 where it is stored until a pre-selected number of clock periods passes. The pre-selected number of clock periods is determined by an external user and programmed in clock generation and control circuit 36. From data register 34, the data is passed at an appropriate time to central processing unit (CPU) 38.
Assuming that the prior art communication system 30 is synchronous, CPU 38 is required to sample the data bus at predetermined clock edges. Therefore, when CPU 38 is operating at a faster frequency than self-timed memory 32, data register 34 is necessary to provide stable data between selftimed memory 32 and CPU 38. Although the prior art implementation illustrated in FIG. 1 provides a useful implementation for insuring the validity of data transferred between self-timed memory 32 and CPU 38, the prior art implementation illustrated fails to facilitate the operation of a memory array at frequencies which are beyond design expectations.
For instance, if the sense and decode precharge signals provided to self-timed memory 32 were not generated and controlled internally and such signals were provided at a frequency which was higher than the design frequency of self-timed memory 32, the access time would not be sufficient for self-timed memory 32 to output valid data. Therefore, even with data register 34, correct data would not be transferred between self-timed memory 32 and CPU 38. This result occurs because self-timed memory 32 has a fixed access time across system clock frequencies.
In a second prior art implementation, consider a first case where the memory system is actually operating at a higher frequency than the CPU. Additionally, consider a second case where software code from an external memory is being ported to on-chip memory; it is desired to slow on-chip memory to emulate a longer access time associated with the external memory. In both cases, the second prior art implementation inserts wait states to accomodate timing sensitive portions of software such that the latency of on-chip operation matches the latency of externally accessed memory. The wait states are inserted prior to on-chip memory access. Again, while this provides a useful solution in some situations, the second prior art implementation also does not facilitate accesses to an on-chip memory at frequencies higher than design expectations.
In a third prior art implementation, control for a non-volatile memory is provided by a fixed algorithm. During a code verification process, control signals for the memory are slowed by a fixed amount when the data processor implementing the non-volatile memory is placed in a special mode of operation. An example is illustrated in the verify operation of the MC68HC908XL36 manufactured by Motorola of Austin, Tex. Again, such control of an on-chip memory, is done only when the data processor is in a special mode of operation and does not allow for flexible control thereof.
Therefore, a need exists for a data processing system which allows for flexible control of a memory to compensate for increased or decreased operating frequencies of a system dock for a data processing system in which the memory is implemented.
Additionally, when memories are implemented in a data processor, an initial access of that memory may require more than one clock cycle. In an application where processing speed and efficiency are paramount, it is desirable to minimize access time required to on-chip memory. A current objective in the data processing industry is to provide a single-docked access to on-chip multi-cycle memory.
Some prior art implementations achieve the aforementioned objective by using interleaved on-chip memory. However, even the initial access to an interleaved multi-cycle memory may still require multiple dock cycles. With the current trend toward integration of system components on-chip and the use of multi-cycle memories thereon, the need to have an initial access to the memory which requires only a single clock is becoming more important.